1. Technical Field
The present invention relates generally to sense amplifier circuits and, more particularly, to sense amplifier circuits.
2. Description of the Related Art
Sense amplifiers for use in memory arrays are well known. A typical sense amplifier is used to detect signals of low power received from the cells within the memory array and convert the signals to power levels compatible with the rest of the system in which the memory is used at a high speed. As memory density increases, the memory cell size and the corresponding cell output signal power is reduced, thereby making the sense amplifier critical for achieving satisfactory power output in the high speed read out of memory cells in a high density memory.
A conventional sense amplifier detects the memory cell output through a differential amplifier, which is highly sensitive, but has very small voltage gain. The output signals from a memory cell are in the form of electric charges, which change the charge level at input junctions of the sense amplifier. In order to obtain a reliable, rapid readout of the memory cell, the input functions of the sense amplifier need to be precharge, between memory cell readouts, to the same voltage level. This process is called equalization.
An example of a sense amplifier of the prior art is shown in FIG. 1. As shown in this figure, the sense amplifier comprises a series of P-FETs and N-FETs. In a FET, the term "source" is used to refer to the end terminal at which carriers are introduced into the conductive path of the FET and the term "drain" is used to refer to the end terminal which receives the carriers from the conductive path. The source and drain are structurally identical and, accordingly, are interchangeable. Complementary signals, cdlt and cdlc, are applied to the sense amplifier on lines 16 and 18 when a memory cell is read out. Complementary signals are a pair of binary signals, each of which represent binary values with opposite signal levels. In the case of the signals cdlt and cdlc, when the cdlt signal is at relatively high voltage when a memory cell is being read out, the cdlc signal will be relatively low and vice versa. In the sense amplifier of FIG. 1, the complementary memory output signals cdlt and cdlc are applied to the gates of N-FETs 17 and 19, respectively. The lower terminals of the FETs 17 or 19, serving as sources, are connected together and through a series connection of N-FETs 21 and 23 to ground. The upper terminals of the N-FETs 17 and 19, serving as drains, are connected through P-FETs 27 and 29, respectively, to voltage source vdd at 3.3 volts. The drain of the N-FET 17 is connected to the gate of the N-FET 21 and is connected to the gates of the P-FETs 27 and 29. An enable signal is connected to the gate of the N-FET 23. The enable signal goes high during the cell readout and goes low between cell readouts. The drain of N-FET 19 is connected to the output junction 30 of the first stage of the sense amplifier and feeds an output amplification stage 32.
The circuit junction 34 at the gate of the N-FET 17 and the circuit junction 36 at the gate of the N-FET 19 are precharge through a circuit comprising N-FETs 38, 40 and 42. The N-FET 38 is connected between the circuit junction 34 and the voltage source vdd. The N-FET 40 is connected between the junction 36 and the voltage source vdd. The N-FET 42 is connected between the circuit junctions 34 and 36. The output stage 32 comprises a P-FET 44, an N-FET 46 and an N-FET 48 connected series between the voltage vdd and ground. The output junction 30 is connected to the gates of the P-FET and the N-FET 46.
An enable_b signal, which is complementary to the enable signal, is applied to the gates of the N-FETs 38, 40 and 42 and renders these FETs conductive between cell readouts and turns these N-FETs off during the cell readouts. As a result, between cell readouts, the junctions 34 and 36 will be shorted together through the N-FET 42 and will be precharge from the vdd source to an equalization voltage of 2.5 volts (3.3 volts minus the threshold voltage of 0.8 volts for the N-FETs 38 and 40). During a memory cell readout, one of the circuit junctions 34 and 36 will be driven high by the complementary signals received from the memory cell and the other junction 34 or 36 will be driven low. When junction 36 is driven high and junction 34 is driven low, the N-FET 19 will be turned on and the N-FET 17 will be turned off. The turning off of the N-FET 17 will cause the gate of the N-FET 21 to go high turning on the N-FET 21 and will cause the gates of the P-FETs 27 and 29 to go high to cause these P-FETs to turn off. Since the enable signal during cell readout will be high, the N-FET 23 will be also conductive. As a result of the N-FETs 19, 21 and 23 being rendered conductive, a conducting path will be established from the output junction 30 to ground and, as a result, the output junction 30 will discharge to a low potential. When the complementary input signals drive input junction 34 high and input junction 36 low, the FET 19 will be cut off and the output junction 30 will remain charged at a high potential. When the output junction 30 is high, conduction through the P-FET in the output stage 44 will be cut off and the N-FET 46 will be rendered conductive. As a result, output connector 50 of the sense amplifier, connected to the junction between the P-FET 44 and the N-FET 46, will be cut off from the vdd voltage and will be connected through the conductive N-FETs 46 and 48 to ground so that the output voltage on connector 50 will go low. Conversely, when the output junction 30 is low, the N-FET 46 will become non-conductive and the P-FET 44 will become conductive. As a result, the output connector 50 will have a conductive path to the voltage source vdd and a high output voltage will be produced.
During the precharging of the input junctions 34 and 36, the sense amplifier consumes power due to heavy capacitive loading on lines 16 and 18. In addition, because the equalization voltage is relative high at 2.5 volts, more time is required to precharge the input junctions and the response of the sense amplifier to the complementary input signals is delayed because the precharge voltage is not close to the threshold at which the FETs 17 and 19 are switched between conductive ands nonconductive states.
For the reasons given above, and for reasons that will become apparent to those skilled in the art from reading and understanding the present specification, there is a need for a sense amplifier which takes less time to precharge the input junctions, which responds more rapidly to the output signals from a memory cell, and which consumes very little power.